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M65KG256AB
256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PRELIMINARY DATA
Features summary
256Mbit SYNCHRONOUS DYNAMIC RAM - Organized as 4 Banks of 4MWords, each 16 bits wide DOUBLE DATA RATE (DDR) - 2 Data Transfers/Clock Cycle - Data Rate: 266Mbit/s (max.) SUPPLY VOLTAGE - VDD = 1.7 to 1.9V (1.8V typical in accordance with JEDEC standard) - VDDQ = 1.7 to 1.9V for Inputs/Outputs SYNCHRONOUS BURST READ AND WRITE - Fixed Burst Lengths: 2, 4, 8, 16 Words - Burst Types: Sequential and Interleaved. - Clock Frequency: 133MHz (7.5ns speed class) - Clock Valid to Output Delay (CAS Latency): 3 at 133MHz - Burst Read Control by Burst Read Terminate and Precharge Commands AUTOMATIC PRECHARGE BYTE WRITE CONTROLLED BY LDQM AND UDQM LOW-POWER FEATURES: - Partial Array Self Refresh (PASR) - Automatic Temperature Compensated Self Refresh (ATCSR) - Driver Strength (DS) - Deep Power-Down Mode - Auto Refresh and Self Refresh LVCMOS Interface Compatible with Multiplexed Addressing OPERATING TEMPERATURE - - 30 to 85C
Wafer

The M65KG256AB is only available as part of a multi-chip package Product.
February 2006
Rev 1.0
1/51
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M65KG256AB
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Inputs (K, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lower/Upper Data Input Mask (LDQM, UDQM) . . . . . . . . . . . . . . . . . . . . . . 10 Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . . . 10 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Mode Register Set command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Extended Mode Register Set command (EMRS) . . . . . . . . . . . . . . . . . . . . . 12 Bank(Row) Activate command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read command (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read with Auto Precharge (READA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Read Terminate command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write command (WRIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write with Auto Precharge command (WRITA) . . . . . . . . . . . . . . . . . . . . . . . 14 Precharge Selected Bank/Precharge All Banks command (PRE/PALL) . . . . 14 Self Refresh Entry command (SELF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Self Refresh Exit command (SELFX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M65KG256AB 3.12 3.13 3.14 3.15 3.16 3.17 Auto Refresh command (REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down Entry command (PDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down Exit command (PDEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Deep Power-Down Entry command (DPDEN) . . . . . . . . . . . . . . . . . . . . . . . 16 Device Deselect command (DESL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 No Operation command (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 5.2 Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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M65KG256AB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bank Selection using BA0-BA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Minimum Delay Between two Commands in Concurrent Auto Precharge Mode . . . . . . . . 18 Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Self Refresh Current (IDD6) in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC Characteristics Measured in Clock Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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M65KG256AB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Simplified Command State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Consecutive Bank(Row) Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read followed by Read in Same Bank and Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read followed by Read in a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read with Auto Precharge AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . 34 Burst Terminate During Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write followed by Write in Same Bank and Row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write followed by Write in a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write operation with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write with Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 1) . . . . . . . . . . . . . . . . . . . . 38 Byte Write AC Waveforms (Data Masking using LDQM/UDQM) . . . . . . . . . . . . . . . . . . . . 39 Mode Register/Extended Mode Register Set Commands AC Waveforms . . . . . . . . . . . . . 40 Read followed by Write using the Burst Read Terminate Command (BST) . . . . . . . . . . . 41 Write followed by Read (Write Completed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Write followed by Read in the same Bank and Row (Write Interrupted). . . . . . . . . . . . . . . 43 Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Auto Refresh Command AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Self Refresh Entry and Exit Commands AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Deep Power-Down Entry Command AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Deep Power-Down Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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1 Summary description
M65KG256AB
1
Summary description
The M65KG256AB is a 256Mbit Double Data Rate (DDR) Low Power Synchronous DRAM (LPSDRAM). The memory array is organized as 4 Banks of 4,194,304 Words of 16 bits each. The device achieves low power consumption and very high-speed data transfer using the 2-bit prefetch pipeline architecture that allows doubling the data input/output rate. Command and address inputs are synchronized with the rising edge of the clock while data inputs/outputs are transferred on both edges of the system clock. The M65KG256AB is well suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers. The device architecture is illustrated in Figure 2: Functional Block Diagram. It uses Burst mode to read and write data. It is capable of two, four, eight or sixteen-Word, sequential and interleaved burst. To minimize current consumption during self refresh operations, the M65KG256AB includes three mechanisms configured via the Extended Mode Register:

Automatic Temperature Compensated Self Refresh (ATCSR) adapts the refresh frequency according to the operating temperature provided by a built-in temperature sensor. Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. The Deep Power-Down (DPD) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array.
The device is programmable through two registers, the Mode Register and the Extended Mode Register:
The Mode Register is used to select the CAS Latency, the Burst Type (sequential, interleaved) and the Burst Length. For more details, refer to Table 7: Mode Register Definition, and to 3.1: Mode Register Set command (MRS) in Section 3: Commands. Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. The Extended Mode Register is used to configure the low-power features (PASR, ATCSR and Driver Strength) to reduce the current consumption during the Self Refresh operations. For more details, refer to Table 8: Extended Mode Register Definition, and to Section 3.2: Extended Mode Register Set command (EMRS) in Section 3: Commands.

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M65KG256AB
Figure 1. Logic Diagram
VDD VDDQ 13 A0-A12 2 BA0-BA1 E RAS CAS K K KE W UDQM LDQM M65KG256AB UDQS LDQS 16 DQ0-DQ15
1 Summary description
VSS
VSSQ
AI10243
Table 1.
A0-A12 BA0-BA1 DQ0-DQ15 K, K KE E W RAS CAS UDQM LDQM UDQS LDQS VDD VDDQ VSS VSSQ
Signal Names
Address Inputs Bank Select Inputs Data Inputs/Outputs Clock Inputs Clock Enable Input Chip Enable Input Write Enable Input Row Address Strobe Input Column Address Strobe Input Upper Data Input Mask Lower Data Input Mask Upper Data Read/ Write Strobe I/O Lower Data Read/Write Strobe I/O Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground
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1 Summary description
M65KG256AB
Figure 2.
K K KE
Functional Block Diagram
Clock Generator TCSR, PASR Extended Mode Register Self Refresh Logic & Timer Internal Row Counter Row Active Row PreDecoders 4 Mb x 16 Bank D 4 Mb x 16 Bank C 4 Mb x 16 Bank B Sense AMP & I/O Gate 4 Mb x 16 Bank A Memory Cell Array Column Decoders Bank Select Column Add Counter ... DQ0 ... I/O Buffer & Logic Row Decoders Row Decoders Row Decoders Row Decoders
E RAS CAS W
StateMachine
Refresh Column Active
...
DQ15 UDQM/LDQM UDQS/LDQS
Column PreDecoders
A0 Address Buffers ... A12 BA1 BA0 ...
Address Registers Burst Counter Burst Length Mode Register
CAS Latency
Data Out Control
ai10242
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M65KG256AB
2 Signal descriptions
2
Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A12)
The A0-A12 Address Inputs are used to select the row or column to be made active. If a row is selected, all thirteen, A0-A12 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used:
During a Read or Write operation: - - If A10 is High (set to `1'), the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0'), the Read or Write cycle does not include an Auto Precharge cycle. If A10 is Low, only the bank selected by BA1-BA0 will be precharged. If A10 is High, all the banks will be precharged.
When issuing a Precharge command: - -
The address inputs are latched at the cross point of K rising edge and K falling edge.
2.2
Bank Select Address Inputs (BA0-BA1)
The Banks Select Address Inputs, BA0 and BA1, are used to select the bank to be made active (see Table 2: Bank Selection using BA0-BA1). When selecting the addresses, the device must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read operation, or to input the data during a write operation.
2.4
Chip Enable (E)
The Chip Enable input, E, activates the memory state machine, address buffers and decoders when driven Low, VIL. When E is High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and BA1BA0, to select the starting column location prior to a read or write operation.
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2 Signal descriptions
M65KG256AB
2.6
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and BA1BA0, to select the starting address location prior to a Read or Write.
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
2.8
Clock Inputs (K, K)
The Clock signals, K and K, are the master clock inputs. All input signals except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge. During read operations, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge. During write operations, UDQM/LDQM and DQ0-DQ15 are referred to the cross point of UDQS/LDQS and VREF, and UDQS/LDQS to the cross point of K rising edge and K falling edge.
2.9
Clock Enable (KE)
When driven Low, VIL, the Clock Enable input, KE, is used to suspend the Clock K, to switch the device to Self Refresh, Power-Down or Deep Power-Down mode. The Clock Enable, KE, must be stable for at least one clock cycle. This means that, if KE level changes on K rising edge and K falling edge with a setup time of tAS, it must be at the same level by the next K rising edge with a hold time of tAH.
2.10
Lower/Upper Data Input Mask (LDQM, UDQM)
Lower Data Input Mask and Upper Data Input Mask are input signals used to mask the written data. UDQM and LDQM are sampled when UDQS/LDQS level crosses VREF. When LDQM is Low, VIL, DQ0 to DQ7 Inputs/Outputs are selected. When UDQM is Low, VIL, DQ8 to DQ15 Inputs/Outputs are selected.
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS)
LDQS and UDQS can be either input or output signals and act as write data strobe and read data strobe respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15, respectively.
2.12
VDD Supply Voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read and Write).
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M65KG256AB
2 Signal descriptions
2.13
VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid certain conditions that would result in data corruption.
2.14
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system ground.
2.15
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). Table 2. Bank Selection using BA0-BA1
Selected Bank Bank A Bank B Bank C Bank D BA0 VIL VIH VIL VIH BA1 VIL VIL VIH VIH
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3 Commands
M65KG256AB
3
Commands
The M65KG256AB recognizes a set of commands that are obtained by specific statuses of Chip Enable, E, Column Address Strobe, CAS, Row Address Strobe, RAS, Write Enable, W, and address inputs. Refer to Table 3: Commands, in conjunction with the text descriptions below. Figure 3: Simplified Command State Diagram shows the operations that are performed when each command is issued at each state of the DDR LPSDRAM.
3.1
Mode Register Set command (MRS)
The Mode Register Set command is used to configure the Burst Length, Burst Type and CAS Latency of the device by programming the Mode Register. The command is issued with KE held High, with BA0, BA1 and A10 set to `0', and E, RAS, CAS and W driven Low, VIL. The value of address inputs A0 to A7 determines the Burst Length, Burst Type and CAS Latency of the device (see Table 7: Mode Register Definition and Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):

The Burst Length (2, 4, 8, 16 Words) is programmed using the address inputs A2-A0 The Burst Type (sequential or interleaved) is programmed using A3. The CAS Latency (3 Clock cycles) is programmed using A6-A4.
It is required to execute a Mode Register Set command at the end of the Power-up sequence. Once the command has been issued, it is necessary to wait for at least two clock cycles before issuing another command.
3.2
Extended Mode Register Set command (EMRS)
The Extended Mode Register Set command is used to configure the low-power features of the device by programming the Extended Mode Register. The command is issued with KE held High, BA0 at `0', BA1 at `1', A10 at `0', by driving E, RAS, CAS and W, Low, VIL. The value of address inputs A0 to A9 determines the Driver Strength, the part of the array that is refreshed during Self Refresh and the Automatic Temperature Compensated Self Refresh feature (see Table 8: Extended Mode Register Definition and Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):

The part of the array to be refreshed (all banks, Bank A and B, Bank A only) during Self Refresh is set using A2-A0. The Driver Strength (full, 1/2 strength, 1/4 strength, 1/8 strength) is set using bits A6-A5 The Automatic temperature Compensated Self Refresh feature is always enabled (A9 set to `0').
It is required to execute an Extended Mode Register Set command at the end of the Power-up sequence. Once the command has been issued, it is necessary to wait for at least two clock cycles before issuing another command.
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M65KG256AB
3 Commands
3.3
Bank(Row) Activate command (ACT)
The Bank(Row) Activate command is used to switch a row in a specific bank of the device from the Idle to the active mode. The bank is selected by BA0 and BA1 and the row by A0 to A12 (see Table 2: Bank Selection using BA0-BA1). This command is initiated by driving KE High, VIH, with E and RAS Low, VIL, and CAS and W High. A minimum delay of tRC is required after issuing the Bank (Row) Activate command prior to initiating Read and Write operations from and to the active bank. A minimum time of tRC is required between two Bank(Row) Activate commands to the same bank (see Figure 6: Consecutive Bank(Row) Activate Command).
3.4
Read command (READ)
The Read command is used to read from the memory array in Burst Read mode. In this mode, data is output in bursts synchronized with the cross points of the clock signals, K and K. The start address of the Burst Read is determined by the column address, A0 to A12, and the bank address, BA0-BA1, at the beginning of the Burst Read operation. A valid Read command is initiated by driving E and CAS Low, VIL, and W and RAS High, VIH.
3.5
Read with Auto Precharge (READA)
This command is identical to the Read command except that a precharge is automatically performed at the end of the Read operation. The precharge starts tRPD (Burst Length/2 clock periods) after the Read with Auto Precharge command is input. A tRAS(min) delay elapses between the Bank (Row) Activate and the Auto Precharge commands. This lock-out mechanism allows a Read with auto Precharge command to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) requirement. The DDR LPSDRAM supports the Concurrent Auto Precharge mode: a Read with autoprecharge can be followed by any command to another active bank, as long as that command does not interrupt the read data transfer, and that all other related limitations apply (e.g. contention between read data and written data must be avoided). Table 4: Minimum Delay Between two Commands in Concurrent Auto Precharge Mode shows the minimum delays between a Read with Auto Precharge command to one bank and a command to a different bank. Refer to Figure 10 for a description of Read operation with Auto Precharge.
3.6
Burst Read Terminate command (BST)
The Burst Read Terminate command is used to terminate a Burst Read operation. It is issued with KE held High, by driving E and W Low and CAS and RAS High. tBSTZ after issuing the Burst Read Terminate command, DQ0-DQ15 and LDQS, UDQS revert to the high impedance state (see Figure 12: Burst Terminate During Read Operation). There is no such command for Burst Write operations.
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3 Commands
M65KG256AB
3.7
Write command (WRIT)
This Write command is used to write to the memory array in Burst Write mode. In this mode, data is input synchronized with the cross points of the clock signals, K and K. The start address of the Burst Write is determined by the column address, A0 to A12, and the address of the selected bank, BA0-BA1, at the beginning of the Burst Read operation. A valid Write command is initiated by driving E, CAS and W Low, VIL, and RAS High, VIH.
3.8
Write with Auto Precharge command (WRITA)
This command is identical to the Write command except that a precharge is automatically performed at the end of the Write operation. The precharge starts tWPD (Burst Length/2 +3 clock periods) after the Write with Auto Precharge command is input. Refer to Figure 16 for a description of Write operation with Auto Precharge.
3.9
Precharge Selected Bank/Precharge All Banks command (PRE/ PALL)
The Precharge Selected Bank and Precharge All Banks are used to place the bank selected by BA0 and BA1 (see Table 2: Bank Selection using BA0-BA1) and all banks in idle mode, respectively. The precharge commands are issued by driving E, RAS and W Low, with CAS and KE held High. The value on A10 determines whether either the selected bank or all the banks will be precharged:

If A10 is High, BA0-BA1 are Don't Care and all the banks are precharged. If A10 is Low when, only the bank selected by BA0-BA1 is precharged.
The bank(s) is/are placed in the Idle mode tRP after issuing the Precharge command. Once the bank is in Idle mode, the Bank (Row) Activate command has to be issued to switch the bank back to active mode. The precharge commands can be issued during Burst Read or Burst Write in which case the Burst Read or Write operation is terminated and the selected bank placed in Idle mode. The device needs to be in Idle mode before entering Self Refresh, Auto Refresh, Power-Down and Deep Power-Down.
3.10
Self Refresh Entry command (SELF)
The Self Refresh Entry command is used to start a Self Refresh operation. Before starting a Self Refresh, the device must be idle. The Self Refresh Entry command is issued by driving KE Low, with E, RAS, and CAS Low, and W High (see Figure 25: Self Refresh Entry and Exit Commands AC Waveforms). During the Self Refresh operation, the internal memory controller generated the addresses of the row to be refreshed. The Self Refresh operation goes on as long as the Clock Enable signal, KE, is held Low.
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3 Commands
3.11
Self Refresh Exit command (SELFX)
The Self Refresh Exit command is used to exit from Self Refresh mode. There are two ways to exit from Self Refresh mode:

Driving KE Low to High, with E High, RAS, CAS and W Don't Care, Driving E Low and RAS, CAS and W High.
Non-read commands can be executed 3tCK + tRC after the end of the Self Refresh operation, where tCK is the Clock period and tRC the RAS Cycle time. See Figure 25 for a description of Self Refresh Exit AC waveforms.
3.12
Auto Refresh command (REF)
This command performs an Auto Refresh. The device is placed in Auto refresh mode from Idle by holding KE High, VIH, driving E, RAS and CAS Low and driving W High. The address bits are "Don't Care" because the addresses of the bank and row to be refreshed are internally determined by the internal refresh controller. The output buffer becomes High-Z after the Auto Refresh has started. Precharge operations are automatically completed after the Auto Refresh. A Bank(Row) Activate, a Mode Register Set or an Extended Mode Register Set command can be issued tRFC after the last Auto Refresh command (see Figure 24: Auto Refresh Command AC Waveforms). The average refresh cycle is tREF (see Table 15: AC Characteristics). To optimize the operation scheduling, a flexibility in the absolute refresh interval is provided. A maximum of eight Auto Refresh commands can be issued to the DDR LPSDRAM and the maximum absolute interval between two Auto Refresh commands 9tREF.
3.13
Power-Down Entry command (PDEN)
The DDR LPSDRAM is caused to enter Power-Down mode from Idle by driving either:

KE Low and E High (other signals are Don't Care), KE Low and RAS, CAS and W High with E Low.
The Power-Down mode continues as long as KE remains Low.
3.14
Power-Down Exit command (PDEX)
The DDR LPSDRAM exits from Power-Down mode by driving KE High.
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3 Commands
M65KG256AB
3.15
Deep Power-Down Entry command (DPDEN)
The device is placed in Deep Power-Down mode by driving KE Low, with E and W Low and RAS and CAS High (see Figure 26: Deep Power-Down Entry Command AC Waveforms). All banks must be precharged or in idle state before entering the Deep Power-Down mode. After the command execution, the device remains in Deep Power-Down mode while KE is low. Deep Power-Down Exit (DPDEX) The M65KG256AB exits Deep Power-Down mode by asserting KE High. A special sequence is then required before the device can take any new command into account: 1. 2. 3. 4. 5. Maintain No Operation status conditions for a minimum of 200s, Issue a Precharge All Banks command (see Section 3.9: Precharge Selected Bank/ Precharge All Banks command (PRE/PALL) for details), Once all banks are precharged and after the minimum tRP delay is satisfied, issue 2 or more Auto Refresh commands, Issue a Mode Register Set command to initialize the Mode Register bits, Issue an Extended Mode Register Set command to initialize the Extended Mode Register bits.
The Deep Power-Down mode exit sequence is illustrated in Figure 27: Deep Power-Down Exit AC Waveforms.
3.16
Device Deselect command (DESL)
When the Chip Enable, E, is High at the cross point of the Clock K rising edge with VREF, all input signals are ignored and the device internal status is held.
3.17
No Operation command (NOP)
The device is placed in the No Operation mode, by driving CAS, RAS and W High, with E Low and KE High. As long as this command is input at the cross point of the Clock K rising edge with the VREF level, address and data input are ignored and the device internal status is held.
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M65KG256AB
Table 3. Commands
Symbol KEn-1(2) KEn
(2)
3 Commands
Command(1)
E
RAS
CAS
W
BA1 BA0
A0-A9, A11-A12 MR/EMR Data(3) MR/EMR Data(3)
A10
Mode Register Set Extended Mode Register Set Bank (Row) Activate Read Read with Auto Precharge Burst Read Terminate Write Write with Auto Precharge Precharge Selected Bank Precharge All Banks Self-Refresh Entry(8) Self Refresh Exit Auto Refresh(8) Power-Down Entry(8)
MRS VIH EMRS ACT READ VIH READA BST WRIT VIH WRITA PRE VIH PALL SELF SELFX REF PDEN VIH VIL VIH VIH VIL VIH VIH VIL VIL VIH VIL VIL VIH VIL VIH VIL VIL X VIL X VIH VIL X VIH X VIH VIH X VIL X VIH VIL X VIH X VIH VIH X VIH X VIH VIL VIL VIH VIL VIH VIL VIH VIL VIL VIH VIH VIL VIH VIH VIL VIH VIL VIH VIL VIH VIH VIH VIL VIL VIH VIH VIH VIL VIL VIL VIL
VIL VIL VIH V V X V V(6) X(7) X X VIH VIH X X VIH X X VIH VIL X X X X V V X V V(6) X(7) X
VIL
Row Address Column Address X Column Address X X X X X X VIL(4) VIH(5) VIL(6) VIH(7) X X X X VIL(4) VIH(5)
Power-Down Exit Deep Power-down Entry(8) Deep Power-down Exit
PDEX DPDEN DPDEX
VIL VIH VIL
VIH VIL VIH
X X X
X X X
1. X = Don't Care (VIL or VIH); V = Valid Address Input. 2. Clock Enable KE must be stable at least for one clock cycle. 3. MR and EMR data is the value to be written in the Mode Register and Extended Mode Register, respectively. 4. If A10 is Low, VIL, when issuing the command, the row remains active at the end of the operation. 5. If A10 is High, VIH, when issuing the command, an automatic precharge cycle is performed at the end of the operation and the row reverts to the Idle mode. 6. If A10 is Low, VIL, when issuing the command, only the bank selected by BA0-BA1 is precharged (BA0-BA1 should be valid). 7. If A10 is High, VIH, when issuing the command, all the banks are precharged and BA0-BA1 are Don't Care. 8. All the banks must be idle before executing this command.
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3 Commands
M65KG256AB
Minimum Delay Between two Commands in Concurrent Auto Precharge Mode
To Command(1) READ or READA Minimum Delay Between the 2 Commands in Concurrent auto Precharge Mode(2) BL/2 CAS Latency (rounded up) + BL/2 1 1 + BL/2 + tWTR BL/2 1 Unit tCK tCK tCK tCK tCK tCK
Table 4.
From Command
READA
WRITE or WRITEA PRE, PALL or ACT READ or READA
WRITEA
WRITE or WRITEA PRE, PALL or ACT
1. This command must be issued to a different Bank from the initial command and must not interrupt it. 2. BL = Burst Length.
Table 5.
Burst Type Definition
Burst Length = 8 Words Burst Length = 16 Words
Burst Length = 2 Burst Length = 4 Words Words Start Addr. (A0-A3) Sequen Inter- Sequen- Inter-tial leaved leaved tial 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
Sequential
Interleaved
Sequential 0-1-2-..D-E-F
Interleaved 0-1-2-..D-E-F 1-0-3-..C-F-E
0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3..D-E-F-0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
2-3-4..E-F-0-1 2-3-0- ..F-C-D 3-4-5..F-0-1-2 4-5-6..0-1-2-3 5-6-7..1-2-3-4 6-7-8..2-3-4-5 7-8-9..3-4-5-6 8-9-A..4-5-6-7 9-A-B..5-6-7-8 A-B-C..6-7-8-9 B-C-D..7-8-9-A 3-2-1-..E-D-C 4-5-6-..9-A-B 5-4-7..8-B-A 6-7-4-..B-8-9 7-6-5-..A-9-8 8-9-A..5-6-7 9-8-A..4-7-6 A-B-8..7-4-5 B-A-9..6-5-4
C-D-E..8-9-A-B C-D-E..1-2-3 D-E-F..9-A-B-C E-F-0..A-B-CD F-0-1..B-C-D-E D-C-F..0-3-2 E-F-C..3-0-1 F-E-D..2-1-0
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M65KG256AB
Figure 3. Simplified Command State Diagram
3 Commands
Extended Mode Register Set
SE LF S R EM
Self Refresh
Mode Register Set
MRS IDLE
SE LF
Ex it
REF
Auto Refresh
CK
D PD D EN ee Ex p P it ow Se e qu r-D en ow ce n
E
CK
E
Power-Down
Deep Power-Down
ACT
ROW ACTIVE
CKE CKE
T BS
Active Power-Down
W rite
W Aut rite wit oP rech h arge
Write
Read
WRITE
Read
PRE
WRITEA
rec
har
ge
Ter
min
atio
n)
aut
d ea R ith d w rge Rea recha oP
READ
POWER-ON
Precharge
Precharge
Automatic Sequence Manual Input Deep Power-Down Exit Sequence
ai11204
PR
E (P
PR E (P h rec eT arg in erm
READA
n) atio
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4 Operating modes
M65KG256AB
4
Operating modes
There are 7 operating modes that control the memory. Each of these is composed by a sequence of commands (see Table 6: Operating Modes for a summary).
4.1
Power-Up
The DDR LPSDRAM has to be powered up and initialized in a well determined manner: 1. 2. After applying power to VDD and VDDQ an initial pause of at least 200s is required before the signals can be toggled. The Precharge command must then be issued to all banks. Until the command is issued KE and UDQM/LDQM must be held High to make sure that DQ0-DQ15 remain high impedance. tRP after precharging all the banks, the Mode Register and the Extended Mode Register must be set by issuing a Mode Register Set command and an Extended Mode Register Set command, respectively. A minimum pause of tMRD must be respected after each register set command. After the two registers are configured, two or more auto Refresh cycles must be executed before the device is ready for normal operation.
3.
4.
The third and fourth steps can be swapped. Refer to Figure 23 for a detailed description of the Power-Up AC waveforms.
4.2
Burst Read
The M65KG256AB is switched in Burst Read mode by issuing a Bank (Row) Activate command to set the bank and column addresses to be read from, followed by a Read command (see sections 3.3: Bank(Row) Activate command (ACT) and 3.4: Read command (READ) for details). Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Burst Read command is issued, the Burst Read operation will be followed by an Auto Precharge cycle. If A10 is Low (set to `0'), the row will remain active for subsequent accesses. Burst Read operations are performed at Word level only. Different Burst Types (sequential or interleaved), Burst Lengths (2, 4, 8 or 16 Words) can be programmed using the Mode Register bits. Only a CAS Latency of 3 clock cycles is available. Refer to Section 5.1: Mode Register description, and to Section 3.1: Mode Register Set command (MRS), for details on the Mode Register bits and how to program them. The Burst Read starts 3tCK + tAC after the Clock K rising edge where the Read command is latched, where tCK is the Clock period and tAC is the access time from K or K. Data Strobe, UDQS/LDQS, are output simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the UDQS/LDQS signals go from High-Z to Low state. This Low pulse is referred to as the Read Preamble. The burst data are then output synchronized with the rising and falling edge of the data strobe. UDQS/LDQS become High-Z on the next clock cycle after the Burst
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M65KG256AB
4 Operating modes
Read is completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as Read Postamble. See Table 5: Burst Type Definition, Table 15: AC Characteristics, Table 16: AC Characteristics Measured in Clock Period, and Figures 9 and 11, for a detailed description of Burst Read operation and characteristics. Burst Read can be terminated by issuing a Burst Read Terminate command (see Section 3.6: Burst Read Terminate command (BST) and Figure 12: Burst Terminate During Read Operation). The interval between Burst Read to Burst Read and Burst Read to Burst Write commands are described in Figures 7, 8 and 20.
4.3
Burst Write
The M65KG256AB is switched in Burst Write mode by issuing a Bank (Row) Activate command to set the bank and column addresses to be written to, followed by a Write command (see sections 3.3: Bank(Row) Activate command (ACT) and 3.7: Write command (WRIT) for details). Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Write command is issued, the Write operation will be followed by an Auto Precharge cycle. If A10 is Low (set to `0'), Auto Precharge is not selected and the row will remain active for subsequent accesses. Burst Write operations can be performed either at Byte or at Word level. The CAS Latency for Burst Write operations is fixed to 1 clock cycle. UDQS/LDQS input act as the strobe for the input data and UDQM/LDQM select the Byte to be written. UDQS/LDQS must be Low tWPRE prior to their first rising edge; and can be changed to High-Z tWPST after their last falling edge. These two periods of time are referred to as Write Preamble and Write Postamble, respectively. See Table 15: AC Characteristics, Table 16: AC Characteristics Measured in Clock Period, and Figures 15, 17, and 18, for a detailed description of Burst Write AC waveforms and characteristics. The interval between Burst Write to Burst Write commands are described in Figures 13, 14, 21 and 22.
4.4
Self Refresh
In the Self Refresh mode, the data contained in the DDR LPSDRAM memory array is retained and refreshed. The size of the memory array to be refreshed is programmed in the Extended Mode Register. Only the data contained in the part of the array selected for Self Refresh will be retained and refreshed. In this respect, this is a power saving feature. The Self Refresh mode is entered and exited by issuing a Self Refresh Entry and Self Refresh Exit command, respectively (see Section 3: Commands). When in this mode, the device is not clocked any more.
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4 Operating modes
M65KG256AB
4.5
Auto Refresh
The Automatic Temperature Compensated Self Refresh mode (ATCSR) is used to refresh the whole DDR RAM array in normal operation mode whenever needed. The device is placed in the Auto Refresh mode by issuing an Auto Refresh command (see Section 3: Commands).
4.6
Power-Down
In Power-Down mode, the current is reduced to the active standby current (IDD3P). The Power-Down mode is initiated by issuing a Power-Down Entry command. tPDEN (1 clock cycle) after the cycle when this command was issued, the DDR LPSDRAM enters into PowerDown mode. In Power-Down mode, power consumption is reduced by deactivating the input initial circuit. There is no internal refresh when the device is in the Power-Down mode. The device can exit from Power-Down tPDEX (1 cycle minimum) after issuing a Power-Down Exit command. See Section 3: Commands for details on the Power-Down Entry and Exit commands.
4.7
Deep Power-Down
In Deep Power-Down mode, the power consumption is reduced to the standby current (IDD7). Before putting the device in the Deep Power-Down mode all the banks must be Idle or have been precharged. The Deep Power-Down mode is entered and exited by issuing a Deep Power-Down Entry and a Deep Power-Down Exit command. See Section 3: Commands for details on the Power-Down Entry and Exit commands.
Table 6.
Operating Modes
KEn-1 VIH VIH VIH VIH VIH
VIH
Operating Mode(1) Burst Read Burst Write Self Refresh Auto Refresh Power-Down Deep Power-Down
KEn VIH VIH VIL VIH VIL
VIL
E VIL VIL VIL VIL VIL VIH
VIL
RAS VIH VIH VIL VIL VIH X
VIH
CAS VIL VIL VIL VIL VIH X
VIH
W VIH VIL VIH VIH VIH X
VIL
A10 VIL(2) VIL(2)
A9, A11 X X X X X
X
A0-A8 Start Column Address Start Column Address
BA0-BA1 Bank Select Bank Select X X X
X
1. X = Don't Care VIL or VIH. 2. If A10 = VIL the Burst Read or Write operation is not followed by an Auto Precharge cycle. If A10 = VIH, the Burst Read or Write operation is followed by an Auto Precharge cycle to the bank selected by BA0-BA1.
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M65KG256AB
5 Registers description
5
Registers description
The DDR Mobile RAM has the two mode registers, the Mode Register and the Extended Mode register.
5.1
Mode Register description
The Mode Register is used to select the CAS Latency, Burst Type, and Burst Length of the device:

The CAS Latency defines the number of clock cycles after which the first data will be output during a Burst Read operation. The Burst Type specifies the order in which the burst data will be addressed. This order is programmable either to sequential or interleaved (see Table 5: Burst Type Definition). The Burst Length is the number of Words that will be output or input during a Burst Read or Write operation. It can be configured as 2, 4, 8 or 16 Words.
The Mode Register must be programmed at the end of the Power-Up sequence prior to issuing any command. It is loaded by issuing a Mode Register Set command (MRS), with BA0-BA1 are set to `00' to select the Mode Register. Table 7: Mode Register Definition, shows the available Mode Register configurations. Table 7.
Address Bits A12-A7 A6-A4
Mode Register Definition
Mode Register Bit MR6-MR4 Register Description CAS Latency Bits (Read Operations) Burst Type Bit 1 001 010 Interleaved 2 Words 4 Words 8 Words 16 Words Value 000000 011 3 Clock Cycles Description
Other configurations reserved 0 Sequential
A3
MR3
A2-A0
MR2-MR0
Burst Length Bit
011 100
Other configurations reserved BA1-BA0 00
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5 Registers description
M65KG256AB
5.2
Extended Mode Register description
The Extended Mode Register is used to program the low-power Self Refresh operation of the device:

Partial Array Self Refresh Driver Strength Automatic Temperature Compensated Self Refresh.
It is loaded by issuing a Extended Mode Register Set command (EMRS) with BA0-BA1 set to `01' to select the Extended Mode Register. Table 8: Extended Mode Register Definition, shows the available Extended Mode Register configurations. Table 8.
Address Bits A12-A10 A9 A8-A7
Extended Mode Register Definition
Mode Register Bit EMR9 Description Value 000 Enabled Reserved Description
0 Automatic Temperature Compensated Self Refresh Bits 1 00 00 01
Full Strength 1/2 Strength 1/4 Strength 1/8 Strength
A6-A5
EMR6-EMR5
Driver Strength Bits 10 11
A4-A3
-
-
00 000 001 All Banks Bank A and Bank B (BA1=0) Bank A (BA0 and BA1 =0)
A2-A0
EMR2-EMR0
Partial Array Self Refresh Bits 010 Other configurations reserved
BA1-BA0
-
-
10
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M65KG256AB
6 Maximum rating
6
Maximum rating
Stressing the device above the ratings listed in Table 9: Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 9.
Absolute Maximum Ratings
Value Symbol TJ TSTG VIO VDD, VDDQ IOS PD Parameter Min Junction Temperature Storage Temperature Input or Output Voltage Supply Voltage Short Circuit Output Current Power Dissipation -30 -55 -0.5 -0.5 50 1.0 Max 85 125 2.3 2.3 C C V V mA W Unit
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7 DC and AC parameters
M65KG256AB
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 10. AC characteristics are measured with driver strength set to "Full Strength" (EMR5EMR6 set to `00'). Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 10.
Symbol VDD VDDQ(2) TJ CL VIL VIH VREF VID VIX VI/ tR
Operating and AC Measurement Conditions
M65KG256AB Parameter(1) Min Supply Voltage Input/Output Supply Voltage Ambient Temperature Load Capacitance Input Pulses Voltages Input Pulses Voltages Input and Output Timing Ref. Voltages Input Differential Voltage (K and K) Input differential Cross Point Voltage (K and K) Input Signal Slew Rate 1.7 1.7 -30 15 0.2 1.6 0.9 1.4 VDDQ/2(2) 1 Typ 1.8 1.8 Max 1.9 1.9 85 V V C pF V V V V V V/ns Units
1. All voltages are referenced to VSS. 2. VDD must be equal to VDDQ.
Figure 4.
AC Measurement I/O Waveform
Clock Timing Reference Voltage K VIX K Output Transition Timing Reference Voltage VDDQ VREF 0V Input Transition Timing Voltage VIH VIL Dt Input Signal Slew Rate = VIH - VIL Dt
AI10238
VREF
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M65KG256AB
Figure 5. AC Measurement Load Circuit
7 DC and AC parameters
DEVICE UNDER TEST
Output
CL
AI11353
Table 11.
Symbol CI1(1)
Capacitance
M65KG256AB Parameter Signal Min K, K Input Capacitance All other input pins Data I/O Capacitance DQ0-DQ15, UDQS/LDQS, LDQM/UDQM 2.0 2.0 3.0 Max 3.0 3.0 4.0 pF pF pF Unit
CI2(1) CIO(1)(2)
1. TJ = 25C; VDD and VDDQ = 1.7 to 1.9V; f = 133MHz; VOUT = VDDQ/2; VOUT = 0.2V. 2. Data Output are disabled.
Table 12.
Symbol ILI ILO VIH(1) VIL(2) VOL VOH VIN VIX VID
DC Characteristics 1
M65KG256AB Parameter Test Condition Min Typ. Max 1.0 1.5 VDDQ+0.3 0.3 0.2 VDDQ-0.2 -0.3 VDDQ+0.3 V V A A 0VVIN VDDQ 0VVOUT VDDQ, DQ0-DQ15 disabled. VIN = 0V VIN = 0V IOUT = 100A 100A IOUT = - -1.0 -1.5 0.8VDDQ - 0.3 Unit
Input Leakage Current Output Leakage Current
Input High Voltage Input Low Voltage Output Low Voltage Output High Voltage Input Voltage Level for K/K inputs Input Differential Cross Point Voltage for K / K inputs Input Differential Voltage for K/ K inputs
V V V V
0.5VDDQ-0.2 0.5VDDQ 0.5VDDQ+0.2 1.0 VDDQ+0.6
1. VIH maximum value = 2.6V (pulse width 5ns). 2. VIL minimum value = 1.0V (pulse width 5ns).
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7 DC and AC parameters
M65KG256AB
Table 13.
Symbol IDD1(2) IDD2P IDD2PS IDD2N
DC Characteristics 2
Parameter Operating Current Precharge Standby Current in PowerDown Mode Test Condition(1)(2) Burst length = 4, one bank active tRC tRC(min), IOL = 0mA KE VIL(max), tCK = 15ns KE VIL(max), tCK = KE VIH (min), E VIH (min), Precharge Standby Current in Non Power-Down Mode tCK = 15ns, Input signals changed once in 2 clock cycles. KE VIH (min), tCK = Input signals are stable Active Standby Current in Power-Down Mode KE VIL(max), tCK = 15ns KE VIL(max), tCK = KE VIH (min), E VIH (min), 3 mA 2 1.5 mA 1.2 M65KG256AB Unit 60 0.8 mA 0.6 mA
IDD2NS IDD3P IDD3PS IDD3N Active Standby Current in Non PowerDown Mode IDD3NS
tCK = 15ns, Input signals are changed once in 2 clock cycles. KE VIH (min), tCK = Input signals are stable tCK tCK (min), IOL = 0mA All banks active Burst Length = 4 tRRC tRRC (min) KE 0.2V KE 0.2V (see Deep Power-Down mode description)
10 mA 7
IDD4(2) IDD5(3) IDD6 IDD7
Burst Mode Current
130
mA
Auto Refresh Current Self Refresh Current Standby Current in Deep Power-down Mode
60 See Table 14 10
mA A A
1. VDD and VDDQ = 1.7 to 1.9V, VSS = VSSQ = 0V. 2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 3. Addresses change only once during tCK.
Table 14.
Self Refresh Current (IDD6) in Normal Operating Mode
Memory Array(1)
Temperature in C
All Banks Typ Max 200 350 550 Typ
2 Banks Max 160 270 400 Typ
1 Bank Max 160 220 320
Unit
-30 TJ 40 40 TJ 65 65 TJ 85
A A A
1. TJ = -30 to 85C, VDD and VDDQ = 1.7 to 1.9V, VSS = VSSQ = 0V; KE 0.2V.
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M65KG256AB
Table 15.
Symbol tAC(2) tAS(3) tAH(3) tCK tDQSCK(2) tDQSHZ(5) tDQSLZ(6) tDQSQ(3) tDV(4) tDS(3) tDH(3) tOHZ(5) tOLZ(6) tRAS tRC tRCD tRRD tRP tREF tSRE tSREX tHZ tLZ tIS tIH
7 DC and AC parameters
AC Characteristics
M65KG256AB(1) Alt Parameter Min Data Output Access Time from K and K Address and Control Input Setup Time Address Control Input Hold Time Clock Cycle Time UDQS/LDQS Access Time from K and K UDQS/LDQS High-Z Time from K and K UDQS/LDQS Low-Z Time from K and K UDQS/LDQS to Data Output Skew Data Output Valid to Data Output Transition Time Data Input and UDQM/LDQM Setup Time Data Input and UDQM/LDQM Hold Time Data Output High-Z Time from K and K Data Output Low-Z Time from K and K RAS Active Time (Bank (Row) Activate to Bank Precharge) RAS Cycle Time (Bank (Row) Activate to Bank Activate in Auto Refresh mode) Delay Time, from RAS Active to CAS Active Delay Time, from RAS Active to RAS Bank Active RAS Precharge Time Average Periodic Refresh Time Self Refresh Exit Time Write Preamble Setup Time 16 0 2 0.9 0.9 1.5 1.5 45 75 30 15 22.5 7.8 6.0 6.0 120000 1.5 1.4 1.4 7.5 1.5 1.5 1.5 6.0 6.0 6.0 0.65 Max 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns Unit
tWPRES
1. The above timings are measured according to the test conditions shown in Table 10: Operating and AC Measurement Conditions. 2. These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.
3. The timing reference level is VREF. 4. tDV defines the delay between two successive transitions of the data output signals, that is when DQ0-DQ15 cross VREF.
5. tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read operation, respectively. They specify when data outputs stop being driven. 6. tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read operation. They specify when data outputs begin to be driven.
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7 DC and AC parameters
M65KG256AB
Table 16.
Symbol
AC Characteristics Measured in Clock Period
M65KG256AB Alt Parameter Min Max tCK tCK 0.55 0.55 tCK tCK ns tCK 1.25 tCK tCK tCK tCK tCK tCK tCK tCK tCK 1.1 0.6 tCK tCK tCK tCK tCK tCK tCK 0.6 tCK tCK tCK tCK tCK Unit
tBSTW(1) tBSTZ(1) tCHW tCLW tDAL tDMD tDQSS tDSS(2) tDSH(2) tDQSH tDQSL tDPE tDPX tMRD tPROZ(1) tRPRE tRPST tRFC tRPD tRWD tWTR tWPRE tWPST(2) tWRD tWPD tWCD tWR tHZP tPDEN tPDEX tCH tCL
Burst Read Terminate Command to Write Command Delay Time Burst Read Terminate Command to Data Output Hi-Z Clock High Pulse Width Clock Low Pulse Width Autoprecharge write recovery and precharge time UDQM/LDQM to Data Input Latency Write Command to First UDQS/LDQS Latching Transition UDQS/LDQS Falling Edge to K Setup Time UDQS/LDQS Falling Edge Hold Time from K UDQS/LDQS High Pulse Width UDQS/LDQS Low Pulse Width Power-Down Entry Time Power-Down Exit Time Mode Register Set Cycle Time Precharge Command to Data Output High-Z Read Preamble Time Read Postamble Time RAS Cycle Time (Auto Refresh to Bank Active in Auto Refresh mode) Delay Time from Read to Precharge Command (same Bank) Delay Time from Read to Write Command (all data output) Write to Read command Delay Write Preamble Data Strobe Low Pulse Width (Write Postamble) Delay Time from Write to Read Command (all data input) Delay Time from Write to Precharge Command (same Bank) Write Command to Data Input Latency Write Recovery Time
3 3 0.45 0.45 2tCK + 22.5 0 0.75 0.2 0.2 0.35 0.35 1 1 2 3 0.9 0.4 15 BL/2(3) 3+BL/2(3) 1 0.25 0.4 2+BL/2(3) 3+BL/2(3) 1 2
1. CAS Latency equals 3 clock cycles. 2. The transition for Low-Z to High-Z occur when the device outputs become floating. No specific reference voltage is given in this document. 3. BL stands for Burst Length.
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M65KG256AB
Figure 6. Consecutive Bank(Row) Activate Command
7 DC and AC parameters
K K tRRD Command ACT A CT NOP PRE NOP ACT NOP
Address
Row 0
Row 1 tRC
Row 0
BA0-BA1 Bank A Active Bank A Active
ai11210
Bank D Active
Precharge Bank A
1. The above figure shows consecutive Bank(Row) Activate commands issued to different banks. A tRRD delay must be respected between two consecutive Bank(Row) Activate commands (ACT) to different banks. If the destination row is already active, the bank must be precharged to close the row; the ACT command can then be issued tRP after the PRE command. 2. Consecutive ACT commands to the same bank must be issued at a tRC interval and separated by a Precharge command (PRE).
Figure 7.
Read followed by Read in Same Bank and Row
K K
Command
ACT
NOP
READ
READ
NOP
Address
Row
Column A Column B
BA0-BA1 Read from Column A DQ0-DQ15 Read from Column B DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
UDQS, LDQS tRCD Bank A Active Note: 1. Burst Length = 4 2. CAS Latency = 3 3. Bank = Bank A Data Read from Column A Data Read from Column B
ai11205
1. The consecutive READ command must be issued after a minimum delay of tCK to interrupt the previous Read operation. 2. To issue the consecutive READ to a different row, precharge the bank (PRE) to interrupt the previous Read operation. tRP after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD after the ACT command.
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7 DC and AC parameters
M65KG256AB
Figure 8.
K K
Read followed by Read in a Different Bank
Command
ACT
NOP
ACT
NOP
READ
READ
NOP
Address
Row 0
Row 1
Column A Column B
BA0-BA1 Read from Read from Column A Column B DQ0-DQ15 DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
UDQS/ LDQS
tRCD Read from Read from Bank D Bank A Data Read from Data Read from Bank D Bank A
Bank A Active Note: 1. Burst Length = 4 2. CAS Latency = 3
Bank D Active
ai11206
1. If the consecutive Read operation targets an active row, the second READ command must be issued after a minimum delay of tCK to interrupt the previous Read operation. 2. If the consecutive Read operation targets an idle row, precharge the bank (PRE) without interrupting the previous Read operation. tRP after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD after the ACT command.
Figure 9.
Read with Auto Precharge
K K tRAS tRCD tRPD READA NOP ACT tRP (min)
Command
ACT
UDQS, LDQS tAC tDQSCK DQ0-DQ15 DO0 DO1 DO2 DO3
Note: Burst Length = 2
Start of Internal Auto Precharge cycle
ai10586
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M65KG256AB
Figure 10. Read with Auto Precharge AC Waveforms
t0 tCK K K tCHW KE tRC E tRAS RAS tCLW tRP t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
7 DC and AC parameters
t11
t12
t13
CAS
W
BA0
BA1
A10
Address tAS tAH LDQM/ UDQM tDQSLZ LDQS/ UDQS tDQSQ DQ0-DQ15 Hi-Z
DO0 DO1 DO2 DO3
tAS tAH
tAS tAH
tAS tAH
tRPRE
tRPST
tRCD
tDV tAC, tDQSCK
tDQSHZ
Bank(Row) Activate in Bank A
Read from Bank A
Precharge in Bank A
AI11212
1. Burst Length = 4 Words, CAS Latency = 3 clock cycles.
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M65KG256AB
Figure 11. Read Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 3)
t0 K K tRCD Command NOP ACT NOP READ NOP t1 t2 t3 t4 t5 t6
A0-A12 BA0-BA1
Row Address
Column Address tRPRE tRPST
UDQS, LDQS(1) tAC tDQSCK DQ0-DQ15(1) DO0 DO1
UDQS, LDQS(2)
DQ0-DQ15(2)
DO0 DO1 DO2 DO3
UDQS, LDQS(2)
DQ0-DQ15(2)
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
Notes: 1. Burst Length = 2 2. Burst Length = 4 3. Burst Length = 8. 4. In all cases, CAS Latency = 3.
ai10552
Figure 12. Burst Terminate During Read Operation
t0 t0.5 K K t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
BST tBSTZ
NOP
UDQS, LDQS
DQ0-DQ15
DO0 DO1
ai10585
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M65KG256AB
Figure 13. Write followed by Write in Same Bank and Row
K K
7 DC and AC parameters
Command
ACT
NOP
WRIT
WRIT
NOP
Address
Row
Column A Column B
BA0-BA1 tRCD DQ0-DQ15 DIA0 DIA1 DIB0 DIB1 DIB2 DIB3
UDQS, LDQS
Bank A Active Note: 1. Burst Length = 4 2. Bank = Bank A
Data Written to Column A
Data Written to Column B
ai11207
1. The consecutive WRIT command must be issued after a minimum delay of tCK to interrupt the previous Write operation. 2. To issue the consecutive WRITE to a different row, precharge the bank (PRE) to interrupt the previous Write operation. tRP after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD after the ACT command.
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7 DC and AC parameters
M65KG256AB
Figure 14. Write followed by Write in a Different Bank
K K
Command
ACT
NOP
ACT
NOP tRCD
WRIT
WRIT
NOP
Address
Row 0
Row 1
Column A Column B
BA0-BA1
DQ0-DQ15
DIA0 DIA1
DIB0 DIB1 DIB2 DIB3
UDQS/ LDQS Bank A Active Note: 1. Burst Length = 4 Bank D Active Data Read from Bank A Data Read from Bank D
ai11208b
1. If the consecutive Write operation targets an active row, the second WRIT command must be issued after a minimum delay of tCK to interrupt the previous Write operation. 2. If the consecutive Write operation targets an idle row, precharge the bank (PRE) without interrupting the previous Write operation. tRP after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD after the ACT command.
Figure 15. Write operation with Auto Precharge
K K tRAS(min) tRCD Command ACT NOP WRITEA NOP ACT tRP
UDQM, LDQM tWPD UDQS, LDQS
DQ0-DQ15
DI0
DI1
DI2
DI3 Start of Internal Auto Precharge cycle
Note: Burst Length = 4
ai10587
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M65KG256AB
Figure 16. Write with Auto Precharge AC Waveforms
t0 tCK K K tCHW KE tRC E tRAS RAS tCLW tRP t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
7 DC and AC parameters
t11
t12
t13
CAS
W
BA0
BA1
A10
Address tAS tAH LDQM/ UDQM tDQSS LDQS/ UDQS tWPRE tDS DQ0-DQ15 Hi-Z
DIN DIN+2 DIN+3
tAS tAH
tAS tAH
tAS tAH
tDQSL
tWPST tDSH
tRCD
tDH tWR
tDQSH
Bank A Active
Write to Bank A
Precharge in Bank A
AI11213b
1. Burst Length = 4 Words, CAS Latency = 1 clock cycle.
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M65KG256AB
Figure 17. Write Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 1)
t0 K K tRCD Command NOP ACT NOP WRITE NOP t1 t2 t3 t4 t5 t6
A0-A12 BA0-BA1
Row Address
Column Address tWPRE
UDQS, LDQS(1) tWPRES DQ0-DQ15(1) DI0 DI1 tWPST UDQS, LDQS(2)
DQ0-DQ15(2)
DI0
DI1
DI2
DI3
UDQS, LDQS(2)
DQ0-DQ15(2)
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
Notes: 1. Burst Length = 2 2. Burst Length = 4 3. Burst Length = 8. 4. In all cases, CAS Latency = 1.
ai10553
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K
tCK
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
K tCHW High tCLW
M65KG256AB
KE
1. Burst Length = 4 Words.
tAH tAH tAH tAH tAS tAS tAS tAS tDQSS tDQSL tWPRE Hi-Z tWPST Hi-Z Lower Byte Read Upper Byte Read Upper Byte Write Upper Byte Write Lower Byte Write Read from Bank D Upper Byte Read Upper Byte Read
AI11218
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM
Figure 18. Byte Write AC Waveforms (Data Masking using LDQM/UDQM)
UDQM
LDQS/ UDQS
DQ0-DQ7
DQ8-DQ15
7 DC and AC parameters
Bank/Row Activate Read in Bank D from Bank D
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7 DC and AC parameters
M65KG256AB
Figure 19. Mode Register/Extended Mode Register Set Commands AC Waveforms
t0 K K High KE tMRD E t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
RAS
CAS
W
BA0-BA1
A10
Address
MR
Data (2)
LDQM/ UDQM
LDQS/ Hi-Z UDQS
DQ0-DQ15 (OUT)
Hi-Z
tRP Precharge (optionnal) Mode Register Set Bank D Active Read to Bank D Precharge Bank D
AI11214
1. To program the Extended Mode Register, BA0 and BA1 must be set to `0' and `1' respectively, and A0 to A11 to the Extended Mode Register Data. 2. MR Data is the value to be written to the Mode Register.
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7 DC and AC parameters
Figure 20. Read followed by Write using the Burst Read Terminate Command (BST)
t0 K K t1 t2 t3 t4 t5 t6 t7 t8
Command
READ
BST
NOP tBSTZ ( tBSTZ)
WRIT
NOP
UDQM, LDQM tBSTZ ( = CL) DQ0-DQ15 DO0 DO1 DI0 DI1 DI2 DI3
UDQS, LDQS Data Output Note: 1. Burst Length = 4 2. CAS Latency = 3 (CL) Data Input
ai11209
1. If the Write operation is performed to the same bank and row than the Read operation, the Burst Read Terminate command (BST) must be issued to terminate the Read operation.The WRIT command can then be issued tBSTW (StBSTW) after the BST command. 2. If the Write operation is performed to the same bank but to a different row, the bank must be precharged to interrupt the Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD after the ACT command. 3. If the Write operation is performed to a different bank and to an active row, the sequence is identical to the one described in Note 1 4. If the Write operation is performed to a different bank and to an idle row, the bank must be precharged independently from the Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD after the ACT command.
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M65KG256AB
Figure 21. Write followed by Read (Write Completed)
t0 K K t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP tWRDmin (3)
READ
NOP
UDQM, LDQM
DQ0-DQ15
DI0
DI1
DI2
DI3
DO0 DO1 DO2
UDQS, LDQS Data Input Note: 1. Burst Length = 4 2. CAS Latency = 3 (CL) 3. tWRD = BL/2 + 2 clock cycles Data Output
ai10838
1. If the Read operation is performed to the same bank and row than the Write operation, the READ command should be performed tWRD after the WRIT command to complete the Write operation. 2. If the Read operation is performed to the same bank but to a different row, the bank must be precharged tWPD after the Write operation. tRP after the Precharge command, issue the ACT command. The READ command can then be issued tRCD after the ACT command. 3. If the Read operation is performed to a different bank and to an active row, the sequence is identical to the one described in Note 1 4. If the Read operation is performed to a different bank and to an idle row, the bank must be precharged independently from the Write operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD after the ACT command.
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M65KG256AB
7 DC and AC parameters
Figure 22. Write followed by Read in the same Bank and Row (Write Interrupted)
t0 K K t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
READ
NOP
UDQM, LDQM
DQ0-DQ15
DI0
DI1
DI2
DO0 DO1 DO2 DO3
UDQS, LDQS Data Input Masked Note: 1. Burst Length = 4 2. CAS Latency = 3 (CL)
ai10839
Data Output
1. UDQM/LDQM must be input 1 clock cycle prior to the READ command to prevent invalid data from being written. If the READ command is input on the next cycle after the WRIT command, UDQM/LDQM are not necessary. 2. If the Read operation is issued to a different row in the same bank, or to an idle row in a different bank, a Precharge command (PRE) must be issued before the READ command. In this case, the Read operation does not interrupt the Write operation. 3. If the Read operation is issued to a different bank, and to an active row, the sequence is identical to the one described in Note 1
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2 Refresh Cycles needed tMRD tMRD
MR Data (1) EMR Data (1)
K
K
High 1 Clock Cycle needed
7 DC and AC parameters
KE
E
Figure 23. Power-Up Sequence
RAS
CAS
W
BA0
BA1
A10
Address
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRP tRFC CBR Auto Refresh tRFC Bank(Row) Activate
AI11211
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Mode Extended Mode CBR Register Set Register Set Auto Refresh
M65KG256AB
Precharge All Banks
M65KG256AB
Figure 24. Auto Refresh Command AC Waveforms
t0 K K High KE t1 t2 t3 t4 t5 t6 tm tm+1 tm+2 tm+3 tm+4 tm+5
7 DC and AC parameters
tm+6
tm+7
tm+8
tm+9
E
RAS
CAS
W
BA0
BA1
A10
Address LDQM/ UDQM
LDQS/ UDQS DQ0-DQ15 (OUT)
Hi-Z Hi-Z
DQ0-DQ15 (IN)
Hi-Z tRP Precharge (optional) Auto Refresh tRFC Bank A Active Read from Bank A
AI11215
1. Burst Length = 4 Words, CAS Latency = 3 clock cycles.
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7 DC and AC parameters
M65KG256AB
Figure 25. Self Refresh Entry and Exit Commands AC Waveforms
t0 K K tAS KE tAH t1 t2 t3 t4 t5 tn tn+1 tn+2 tm tm+1 tm+2 tm+3 tm+4 tm+5
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/ UDQM Hi-Z
UDQS/ LDQS DQ0-DQ15 (OUT) DQ0-DQ15 (IN)
Hi-Z Hi-Z tRP Precharge (optional) Self Refresh Entry Self Refresh Exit tSREX Bank A Active Read to Bank A
ai11216
1. Burst Length = 4 Words.
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M65KG256AB
Figure 26. Deep Power-Down Entry Command AC Waveforms
t0 K K KE t1 t2 t3 t4
7 DC and AC parameters
t5
E
RAS
CAS
W
A10
UDQM/ Low LDQM DQ0-DQ15 Hi-Z tRP Precharge All Banks Deep Power-Down Entry
ai10847
1. BA0, BA1 and address bits A0 to A11 (except A10) are `Don't Care'. Upper and Lower Data Input Mask signals, UDQM and LDQM are Low, VIL.
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t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 2 Refresh Cycles needed tMRD tMRD
MR Data (1) EMR Data (1)
t0
t1
K
K
1 Clock Cycle needed
7 DC and AC parameters
KE
High Level nedeed
E
RAS
CAS
Figure 27. Deep Power-Down Exit AC Waveforms
W
BA0
BA1
A10
Address
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRP tRFC Auto Refresh tRFC Bank/Row Activate
AI11217
200s
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Mode Extended Mode Auto Refresh Register Set Register Set
M65KG256AB
Deep Power-Down Exit
Precharge All Banks
M65KG256AB
8 Part numbering
8
Table 17.
Example:
Part numbering
Ordering Information Scheme
M65KG256AB 8 W 8
Device Type M65 = Low-Power SDRAM
Mode K = Wafer Form
Operating Voltage G = VDD = VDDQ = 1.8V, DDR LPSDRAM, x16 Array Organization 256 = 4 Banks x 4Mbit x 16
Number of Chip Enable Inputs A = One Chip Enable
Die Version B = B-Die
Speed 8 = 7.5ns
Delivery Form W = Wafer Form
Temperature Range 8 = 30 to 85C
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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9 Revision history
M65KG256AB
9
Revision history
Date 09-Feb-2006 Revision 1.0 First Issue. Changes
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M65KG256AB
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